FPGA Based Design and Implementation of Low Cost High Performance Generalised Cascaded Asymmetric Multilevel Inverter

In this work, initially a new topology for sub multilevel inverter is introduced and then series connection of the sub multilevel inverters is developed as a generalized fifteen level multilevel inverter. This multilevel inverter has been analyzed in asymmetric conditions with different values of DC sources. This new multilevel inverter topology has the advantage of reduced number of switches compared to a conventional H bridge multilevel inverter. The required gate pulses for the switches are given by level shifted carrier based Pulse width modulation technique. This highly conventional technique is based on the comparison of a sinusoidal reference with carrier signals. This modulation scheme for generating gate pulses for the switches is implemented using Spartan 6 FPGA processor. The main advantage of this is the ability to generate SPWM waveform in real time using control algorithm in the FPGA processor. This reduces the computational time required to determine the switching times for inverter legs, making the system more suitable for real time implementation for larger drives. It also focuses on getting a more output voltage level with reduced number of switches. The multilevel inverter is simulated using MATLAB/ SIMULINK software for fifteen levels of step voltages with different DC sources and implemented with both R and RL loads and power quality analysis has been done.